1. Technical Field of the Invention
The present invention relates to hierarchical filters such as finite impulse response (FIR) and, in particular, to a digital matched filter.
2. Description of Related Art
With reference to the known cell search procedure in the UMTS-FDD standard, slot synchronization is acquired by correlating an input signal (S) with a 256-chip long sequence primary synchronization code (PSC) at the beginning of each time slot. More specifically, two data channels, one in phase (I) and one quadrature phase (Q), are filtered by an (N×M)-tap finite impulse response filter (in particular, N=M=16 for UMTS-FDD) to the primary synchronization code. The filtered output signal, or a direct transformation thereof (for example, an energy computation) is then stored in memory and accumulated over several time slots. An energy peak in the accumulated output signal corresponds to the possible starting location of a time slot.
Referring now to FIG. 1, there is shown a top level block diagram of a cell searcher 10. The searcher includes a digital matched filter (DMF) 12 and a maximum energy finder (MEF) 14. The digital matched filter 12 correlates the incoming samples (both I and Q) with the primary synchronization code pattern, and outputs an energy 16. This energy may be calculated for output as the correlation square norm or as a non-euclidian distance (such as a sum of absolute values). These calculated energies 16 are then delivered to the maximum energy finder 14. The maximum energy finder 14 operates to accumulate the energies 16 over time for the purpose of increasing signal to noise ratio (SNR) and the likelihood of detecting peak values. The highest accumulated energies are then selected by the maximum energy finder 14 as corresponding to the best correlation phases.
The cell search 10 further includes a processor interface (I/F) 18 that receives data from the digital matched filter 12 and maximum energy finder 14 for output and use elsewhere. For example, the interface 18 collects and delivers energy peaks, timings, noise estimates, and the like data as known by those skilled in the art, including information relating to the performed cell search step 1, step 2 and step 3 tasks for initial cell search and acquisition. As an example, the interface 18 may comprise an advanced peripheral bus (APB) interface. It will also be recognized by those skilled in the art that if the searcher 10 is implemented wholly in software, then a bus interface would not be necessary, and instead could be replaced by a software controller (as alternatively illustrated in FIG. 1).
It is common for at least the digital matched filter 12, if not the entire cell searcher 10 (and perhaps further the entire digital baseband circuit), to be manufactured as an integrated circuit (one or more integrated circuits may be implicated, perhaps with other functions as well). This integrated circuit is then utilized in a mobile environment and powered by a battery. Because battery power supply resources are limited in such applications, there is a need in connection with any implementation of the filter 12 for use in a mobile environment (in either hardware or software) to reduce power consumption.
As is also well known to those skilled in the art, the digital matched filter 12, especially one of the large size used in the cell searcher 10, takes up a significant amount of area when implemented in silicon. There is accordingly a need, not only for the silicon chip (or chip set) associated with the modem/cell searcher, but also in connection with any implementation of a hierarchical filter in silicon, to reduce silicon area consumption.
The present invention provides an improved architecture design for a digital matched filter that addresses the foregoing concerns.